Dual latch architecture for reducing clock feedthrough in...

Details Dual latch architecture for reducing clock feedthrough in... Dual latch architecture for reducing clock feedthrough in...

H - Electricity

03

M

354/97

H03M 1/06 (2006.01) H03M 1/00 (2006.01)

Patent

CA 1257397

Abstract A high speed monolithic current switching digital- to-analog converter (DAC) is provided. The DAC includes input level shift clock and data drivers, differential dual latches, differential multiplexers and high speed current switching cells. Utilizing complementary clocks at one-half the input data rate, data is effectively latched at each transition or edge of the clock pulse rather than at only the positive (or negative) going edge of the clock. Thus, feedthrough of the previously unused clock edge and pertur- bation in the DAC output caused by the unused clock edge is eliminated.

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