Dual-mode cmos integrated imager

H - Electricity – 04 – N

Patent

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H04N 3/15 (2006.01) H04N 5/335 (2006.01)

Patent

CA 2410537

A CMOS integrated imager system (17) formed on a single IC having a first mode in which the system operates using on-chip logic (31) to generate complex timing on-chip and to use that timing for operation and also having a second mode of operation in which the on-chip logic is bypassed (29) and an external timing (19) system is used.

L'invention concerne un système d'imagerie (17) à intégration CMOS formé sur un seul circuit intégré, lequel système possède un premier mode de fonctionnement, où le système fonctionne selon une logique (31) réalisée sur la puce pour générer une synchronisation complexe intégrée et utiliser cette synchronisation aux fins du fonctionnement ; et un second mode de fonctionnement, où la logique réalisée sur la puce est court-circuitée (29) et où l'on utilise un système de synchronisation (19) externe.

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