G - Physics – 11 – C
Patent
G - Physics
11
C
352/18, 354/231,
G11C 8/00 (2006.01) G11C 7/00 (2006.01) G11C 7/22 (2006.01) G11C 8/16 (2006.01) H04N 5/44 (2006.01)
Patent
CA 1310743
RCA 84,124 Abstract of the Disclosure A dual port digital memory system, which includes integral memory sequencing circuitry, is controlled by a bit-serial address and control signal. The address and control signal, which includes a data read address, a data write address and a control value, is serially loaded into a shift register. The address sequencing circuitry loads the read and write address values into integral read and write address registers and, based on the control value, initiates respective read and/or write operations.
557611
Christopher Todd J.
Hirahata Shigeru
Christopher Todd J.
Craig Wilson And Company
Hirahata Shigeru
Hitachi Ltd.
Rca Licensing Corporation
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