Dual resistivity mos devices and method of fabrication

Details Dual resistivity mos devices and method of fabrication Dual resistivity mos devices and method of fabrication

G - Physics

11

C

356/128, 352/82.

G11C 11/34 (2006.01) H01L 21/033 (2006.01) H01L 21/8234 (2006.01) H01L 27/092 (2006.01) H01L 27/105 (2006.01)

Patent

CA 1151295

Abstract of the Disclosure A method of forming combination CMOS field effect transistors optionally with a charge transfer device in a single substrate. Different resistivities in the P type wells of the substrate are formed by a combination of masks; a high energy low dosage ion implantation of impurity passes through one mask but not the other, and a low energy high dosage ion implantation of the impurity is stopped by both masks. A significant number of fabrication steps is thus saved, and the devices so fabricated are threshold and field voltage compatible.

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