Duty cycled control implemented within a frequency synthesizer

Details Duty cycled control implemented within a frequency synthesizer Duty cycled control implemented within a frequency synthesizer

H - Electricity

03

L

H03L 7/16 (2006.01) H03B 1/00 (2006.01)

Patent

CA 2159762

A programmable frequency synthesizer comprised of a phase locked loop (PLL) including a current controlled oscillator (ICO), a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate, a reference source of signals, a phase-frequency detector for receiving signals from the reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and apparatus for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied.

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