Dynamic addressing for variable track length cache memory

G - Physics – 06 – F

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G06F 9/00 (2006.01) G06F 12/00 (2006.01) G06F 12/08 (2006.01) G06F 13/00 (2006.01) G11C 7/00 (2006.01) G11C 8/00 (2006.01) G11C 15/00 (2006.01) G11C 17/00 (2006.01) G11C 19/00 (2006.01) G11C 21/00 (2006.01) G11C 27/00 (2006.01)

Patent

CA 1253627

STC-155 ABSTRACT OF THE DISCLOSURE A data storage system includes a host computer and magnetic disk units of diverse types. A solid state cache memory stores data records at addresses which are generated by a microprocessor in the cache manager. These addresses include a beginning of track address and an end of track address which span a frame having enough memory locations to store an entire track for a particular type of disk unit.

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