Dynamic cmos current surge control

Details Dynamic cmos current surge control Dynamic cmos current surge control

H - Electricity

03

K

328/127

H03K 19/00 (2006.01) G06F 1/30 (2006.01)

Patent

CA 1281088

DYNAMIC CMOS CURRENT SURGE CONTROL Abstract Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due tothe floating input node of complementary inverters causing current to flow briefly before clock pulses arrive, The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node, An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.

558079

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