Dynamic control of a phase-locked loop

Details Dynamic control of a phase-locked loop Dynamic control of a phase-locked loop

H - Electricity

03

L

H03L 7/00 (2006.01) H03L 7/06 (2006.01) H03L 7/08 (2006.01) H03L 7/093 (2006.01) H03L 7/107 (2006.01)

Patent

CA 2460107

A Phase-locked Loop (PLL) (204) that is dynamically and automatically altered in response to changes in the jitter of the input is disclosed. The Analysis Block (304) receives one or more inputs from the PLL operation. The output of the Analysis Block (304) triggers a change in the Parametric Control Block (308) which in turn imparts changes on the gains of one or more of the various components or the value of .omega.N of the PLL Low Pass Filter (116). The dynamic change to at least one parameter of the PLL adjusts the tradeoff between removing as much of the jitter as possible and having a responsive system that has a reduced risk of buffer underflow or overflow. This abstract is provided as a tool for those searching for relevant disclosures, and not as a limitation on the scope of the claims.

L'invention concerne une boucle à phase asservie (PLL) (204) altérée de manière dynamique et automatique, en réponse à des variations dans la gigue d'un signal d'entrée. Le fonctionnement de la PLL produit un ou plusieurs signaux d'entrée reçus par un bloc d'analyse (304). Un signal de sortie du bloc d'analyse (304) déclenche une variation dans un bloc de commande paramétrique (308) qui à son tour produit des variations sur les gains d'un ou de plusieurs des divers composants ou sur la valeur de ?¿N? du filtre passe-bas (116) de la PLL. La variation dynamique d'au moins un paramètre de la PLL règle le compromis entre le fait d'éliminer le plus de gigue possible et d'avoir un système sensible présentant un risque réduit de dépassement de capacité inférieur ou supérieur du tampon.

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