Dynamic device address assignment mechanism for a data...

Details Dynamic device address assignment mechanism for a data... Dynamic device address assignment mechanism for a data...

G - Physics

06

F

354/233

G06F 3/00 (2006.01) G06F 12/06 (2006.01) G06F 15/00 (2006.01)

Patent

CA 1158778

BC9-80-012 ABSTRACT DYNAMIC DEVICE ADDRESS ASSIGNMENT MECHANISM FOR A DATA PROCESSING SYSTEM A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appear- ance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.

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