Dynamic differential logic circuits

Details Dynamic differential logic circuits Dynamic differential logic circuits

G - Physics

06

F

354/182

G06F 7/52 (2006.01) H03K 19/173 (2006.01) H03K 19/21 (2006.01)

Patent

CA 1168759

ABSTRACT The disclosure teaches various logic circuits operating with Dynamic Differential Logic (DDL). In a particular embodiment MOS transistors of n-channel type are used with circuits arranged to avoid any dc path from clock input to ground. The input capacitance of the active devices is used for temporary storage thereby reducing circuit complexities. Coupling between stages is provided by clock driven transistors connected so that the transistor at the higher voltage side cuts off early in the period of clock pulse decay, thereby isolating adjacent stages without unnecessary delay. The use of such circuits in array processors is described.

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