Dynamic memory controller for single-chip microprocessor

Details Dynamic memory controller for single-chip microprocessor Dynamic memory controller for single-chip microprocessor

G - Physics

06

F

354/237

G06F 12/16 (2006.01) G06F 9/48 (2006.01) G06F 12/02 (2006.01) G11C 11/406 (2006.01)

Patent

CA 1225162

DYNAMIC MEMORY CONTROLLER FOR SINGLE-CHIP MICROPROCESSOR Abstract of the Disclosure A controller for interfacing a single-chip microcomputer with external dynamic random-access memory, includes a subcircuit for generating a column-address strobe at a time after a row-address strobe is generated, and also includes a multiplexing subcircuit for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8-bit dynamic memory inputs, prior to receipt of the associated row-address or column-address strobe. The microprocessor utilizes the strobe- generation and multiplexing subcircuits to burst- refresh the dynamic memory, in one presently preferred embodiment. In another presently preferred embodiment, lines from an additional microprocessor output port are utilized with a resettable binary counter and a multiplicity of buffers, to count through the range of row addresses in cyclic fashion, with each address being incremented after the previously-addressed row of memory cells has been refreshed.

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