Dynamic memory refresh and parity checking circuit

Details Dynamic memory refresh and parity checking circuit Dynamic memory refresh and parity checking circuit

G - Physics

06

F

354/224

G06F 11/10 (2006.01) G06F 11/14 (2006.01) G06F 13/28 (2006.01) G11C 7/10 (2006.01) G11C 11/4096 (2006.01)

Patent

CA 1240066

ABSTRACT A circuit for use in conjunction with a microprocessor for refreshing, checking and correcting data signals stored in a dynamic memory. The circuit utilizes a direct memory access controller for transferring data signals stored in successive locations of the dynamic memory to a non-existent peripheral. Data signals appearing on a data bus as a result of the data transfer, are applied to a parity checking circuit for generating an interrupt signal to the microprocessor in response to detection of parity errors in the data signal. The microprocessor then performs a data recovery routine in which correct versions of the data signal stored in a non-volatile memory, are transferred for storage in the dynamic memory under control of a microprocessor. Parity errors in data signals stored in the dynamic memory are thus corrected prior to being accessed by the microprocessor.

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