G - Physics – 06 – F
Patent
G - Physics
06
F
354/237
G06F 12/16 (2006.01) G11C 7/00 (2006.01) G11C 11/406 (2006.01)
Patent
CA 1279730
DYNAMIC RANDOM ACCESS MEMORY REFRESH CIRCUIT SELECTIVELY ADAPTED TO DIFFERENT CLOCK FREQUENCIES ABSTRACT OF THE INVENTION This invention is a dynamic RAM memory refresh circuit for use in conjunction with a microprocessor. In a small telecommunication switching system, a microprocessor shares access to memory with the dynamic RAM refresh circuit. Since circuitry size is of paramount importance, this circuit is suitable for implementation with CMOS gate array technology. Since memory access is shared by the microprocessor and the dynamic RAM refresh circuit, processor through-put in affected. However, due to the speed of the dynamic RAM refresh circuit, the microprocessor real-time is degraded only from 2 to 5 percent. A row of dynamic RAM memory is refreshed during each memory access by the refresh circuit, so that during a 2 millisecond interval all dynamic RAN memory is refreshed. In addition, the dynamic RAM refresh circuit provides a strapping option to allow operation of the refresh circuit in conjunction with microprocessors of different clock frequency.
519970
Gte Communication Systems Corporation
R. William Wray & Associates
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