Dynamic power saving memory architecture

Details Dynamic power saving memory architecture Dynamic power saving memory architecture

G - Physics

11

C

G11C 5/02 (2006.01) G11C 7/10 (2006.01) G11C 7/18 (2006.01) G11C 8/12 (2006.01)

Patent

CA 2726279

A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and configured to control each of the word lines. The memory also includes multiplexers coupled to each of the interface ports. The multiplexers are configured to cause the selection of one of the sub-arrays based upon an address of a memory cell received at one or more of the interface ports.

Une mémoire comprend de multiples ports d'interface. La mémoire comprend également au moins deux sous-réseaux ayant chacun une instance de toutes les lignes de bit de la mémoire et dune partie des lignes de mot de la mémoire. La mémoire a un décodeur commun couplé aux sous-réseaux et configuré pour commander chacune des lignes de mot. La mémoire comprend également des multiplexeurs couplés à chacun des ports d'interface. Les multiplexeurs sont configurés pour provoquer la sélection de l'un des sous-réseaux sur la base d'une adresse d'une cellule de mémoire reçue par un ou plusieurs des ports d'interface.

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