Dynamic ram organization for reducing peak current

Details Dynamic ram organization for reducing peak current Dynamic ram organization for reducing peak current

G - Physics

11

C

352/82.3

G11C 11/40 (2006.01) G11C 11/404 (2006.01) G11C 11/4063 (2006.01) G11C 11/4091 (2006.01)

Patent

CA 1127762

21. DYNAMIC RAM ORGANIZATION FOR REDUCING PEAK CURRENT Abstract of the Disclosure An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub arrays. During an operating cycle latching of the sense amplifiers in the sub?arrays is staggered to avoid coincidence of current peaks each arising when the sense amplifiers in one of the sub arrays are simultaneously latched. Latching takes place first in a sub?array in which a cell is selected. Recovery of the column conductors in the sub? arrays is also staggered to avoid coincidence of current peaks each occurring when one of the sub?arrays is recovered. The sub-array in which a cell is selected is recovered last.

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