G - Physics – 06 – F
Patent
G - Physics
06
F
354/237
G06F 12/02 (2006.01) G06F 11/00 (2006.01) G06F 13/38 (2006.01) G11C 11/406 (2006.01) G06F 11/22 (2006.01)
Patent
CA 1213675
DYNAMIC RANDOM ACCESS MEMORY REFRESH CONTROL SYSTEM Abstract of the Disclosure A system and method are disclosed for automatically refreshing a dynamic random access memory (DRAM) under a plurality of different opera- tional conditions of an associated processor. In a preferred embodiment of the invention, when the processor is normally executing instructions it gene- rates active signals. These active signals enable a generator circuit to generate timing signals. A hidden refresh circuit uses status signals and a first part of these timing signals to generate a refresh pulse during an opcode fetch cycle of each instruction being executed by the processor. A control circuit uses each refresh pulse and a second part of the timing signals to generate a row refresh signal to refresh a row in the DRAM indicated by a row address from a counter and a row address clock to increment the counter to the next row in the DRAM to be re- freshed by the following row refresh signal. When a keep alive circuit senses that the processor has not run for a preselected period of time due to the in- circuit use of a piece of test equipment, the keep- alive circuit generates pulses to enable the hidden refresh circuit to cause the control circuit to peri- odically refresh the DRAM until after the processor starts running again. When a halt/power-down circuit senses that the processor is executing a HALT instruc- tion, it forces the processor to branch off into a subroutine to execute a preselected number of instruc- tions to refresh an associated number of rows of memory in the DRAM before allowing the processor to return to its HALT instruction. This operation peri- odically repeats until the processor has completed its HALT instruction. When the halt/power-down circuit senses an impending power failure, it switches the system over to a back-up, power down mode of operation and also generates signals to enable the control circuit to continuously refresh the DRAM until after power is restored.
463315
Hughes Robert C.
Kappeler Ronald P.
Ncr Corporation
Smart & Biggar
LandOfFree
Dynamic random access memory refresh control system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic random access memory refresh control system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory refresh control system will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1237287