Dynamic ttl input comparator for cmos devices

Details Dynamic ttl input comparator for cmos devices Dynamic ttl input comparator for cmos devices

H - Electricity

03

K

328/84

H03K 19/094 (2006.01) H03K 3/356 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 1199686

ABSTRACT OF THE DISCLOSURE . A CMOS buffer for the dynamic translation of input signals at TTL levels to corresponding signals at CMOS levels. A reference voltage at a level between the 0.8 volt maximum TTL "O" input level and the 2.4 volt minimum "1" input level is generated by charge distribution between capacitors. This reference level is compared with input signal level in a dynamic comparator comprised of a CMOS cross-coupled latch to produce output signals at CMOS levels that correspond to the TTL input signals.

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