Earom cell matrix and logic arrays with common memory gate

Details Earom cell matrix and logic arrays with common memory gate Earom cell matrix and logic arrays with common memory gate

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G11C 7/00 (2006.01) G11C 11/40 (2006.01) G11C 16/04 (2006.01) G11C 16/10 (2006.01) G11C 16/12 (2006.01) H01L 29/792 (2006.01) H03K 19/177 (2006.01)

Patent

CA 1179428

-30- EAROM CELL MATRIX AND LOGIC ARRAYS WITH COMMON MEMORY GATE Abstract of the Disclosure A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line. The logic state stored in the cell is defined by the presence or absence of a conductive path through the cell when all three gates are biased to their read mode levels. A unitary configuration of the cell includes a single substrate, with a channel defined between doped node regions. Electrically isolated gate electrodes of the three transistors are symmetrically disposed adjacent each other over the channel to control its conductivity in segments. The cells are amenable to being grouped in arrays, while retaining the independence of the high voltage memory line and the flexibility of individual row and column addresses.

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