Echo canceller employing dual-h architecture having variable...

Details Echo canceller employing dual-h architecture having variable... Echo canceller employing dual-h architecture having variable...

H - Electricity

04

B

H04B 3/23 (2006.01) H04M 9/08 (2006.01)

Patent

CA 2592930

An echo canceller circuit comprises a digital filter having adaptive tap coefficients that simulate an echo response, the adaptive tap coefficients being updated at times using during each such time an adaptive process having an adaptive gain and a channel condition detector that lowers the adaptive gain a variable amount depending on the amount of background noise, the echo canceller circuit being responsive to the adaptive tap coefficients to generate an echo-compensated signal. A method for processing an echo response is also provided

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