Efficient address test for large memories

Details Efficient address test for large memories Efficient address test for large memories

G - Physics

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G11C 29/00 (2006.01) G11C 29/02 (2006.01) G11C 29/10 (2006.01) G11C 29/18 (2006.01) G11C 29/42 (2006.01) G06F 11/00 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1291269

Abstract A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage word. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accessed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart. TU986-012

556026

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