Electric balances having digitisation error reducing loop

Details Electric balances having digitisation error reducing loop Electric balances having digitisation error reducing loop

G - Physics

01

G

265/5, 328/83

G01G 7/00 (2006.01)

Patent

CA 1121835

ABSTRACT OF THE DISCLOSURE A control circuit which feeds a control signal to a comparator to determine the duration of pulses of constant current to the compensating means for an electric balance having electromagnetic coil means, is modified to include an additional entirely loop, to minimise digitisation error arising from the need to cut off each current pulse just after the comparator produces a cut-off signal. The fluctuation of the display when the scale operates at high resolution in relation to the frequency of timing marking used for counting the lengths of current pulses and producing a digital indication is reduced by including an integrator arranged to be controlled by the synchroniser and to supply an error voltage combined with the control signal voltage at the input to the comparator. The mechanical inertia of the load-receiver is excluded sufficiently so that digitisation error can be cancelled out relatively rapidly.

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