Electrical isolation in integrated circuits

Details Electrical isolation in integrated circuits Electrical isolation in integrated circuits

H - Electricity

01

L

H01L 27/02 (2006.01) H01L 21/98 (2006.01) H01L 27/092 (2006.01)

Patent

CA 2124687

2124687 9409515 PCTABS00032 A back biasing technique is provided for increasing the field inversion voltage between adjacent MOS transistors and for reducing parasitic capacitances in an integrated circuit. The use of a charge pump is avoided by connecting the body portion (11) of the MOS transistors to ground and the sources (22) of the MOS transistors to the anode (27) of a diode, the cathode (26) of which are connected to a reference voltage such as to ground. In this manner, the sources are back biased relative to the material in which they are formed by a diode forward voltage drop. This technique is particularly applicable to CMOS circuits operating form a 3.3 volt supply, with p-well (15) doping densities in excess of 1x1017 atoms/cm3.

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