Electrically erasable nonvolatile memory

Details Electrically erasable nonvolatile memory Electrically erasable nonvolatile memory

G - Physics

11

C

G11C 16/14 (2006.01)

Patent

CA 2341102

A nonvolatile memory cell (10) which is highly scalable includes a cell formed in a triple wall. The control gate (12) is negatively biased. By biasing the P- well (30) and drain (or source) (18) positively within a particular voltage range when erasing, GIDL current and degradation from a hole trapping can be diminished and hence scalable technology may be achieved.

L'invention concerne une cellule de mémoire non volatile (10) à variabilité élevée; elle comprend une cellule formée dans une paroi triple. La grille de commande (12) est polarisée négativement. En polarisant positivement le puits de type P (30) et le drain (ou la source) (18) dans les limites d'une plage de tension déterminée lors de l'effacement, on réduit le courant de fuite de drain induit par la grille et l'on diminue la dégradation due à la capture par trous, ce qui permet de mettre en place une technologie à géométrie fortement variable.

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