H - Electricity – 05 – K
Patent
H - Electricity
05
K
H05K 9/00 (2006.01) H05K 1/02 (2006.01)
Patent
CA 2146139
An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.
Technique de réduction EMR utilisant des traces et traversées conductrices mises à la masse qui circonscrivent les plans internes de circuits imprimés. Les traversées conductrices suivent un trajet sinueux en périphérie, encerclant les traces conductrices de signal de chaque couche d'un circuit imprimé. Le plan de masse est étendu pour englober et mettre électriquement à la masse chacune des traversées. Pour chaque plan conducteur de signal, une trace conductrice est acheminée et connectée à chacune des traversées, formant un bouclier à la masse autour des traces conductrices de signal dans le plan conducteur de signal. Pour les plans d'alimentation, une trace conductrice connecte les traversées conductrices et forme un bouclier à la masse autour des plans d'alimentation. Un trajet non conducteur, entre le plan d'alimentation et la trace conductrice du plan d'alimentation, assure l'isolation électrique entre les tensions du plan d'alimentation et la trace conductrice mise à la masse.
Compaq Computer Corporation
Finlayson & Singlehurst
LandOfFree
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