Electronic circuit for generating error detection codes for...

H - Electricity – 03 – M

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354/67

H03M 13/00 (2006.01) H03M 13/15 (2006.01)

Patent

CA 2037219

An electronic circuit, for generating error detection codes from digital signals organized into serial data blocks, in which the error code is derived from the coefficients of a remainder polynomial obtained from the division by a suitable divisor polynomial of a dividend polynomial whose coefficients are the bits of each serial block, is implemented by feedback through adders within shift register. A reset of the register necessary at the beginning of each serial data block and the loading of a first data bit of the block are both performed in a single clock interval, by using flip-flops to form the register which have alternative inputs one of which is used during reception of the first bit of a block to handle that bit and place the remainder of the register in a defined condition, and the other of which is used during processing of the remaining bits.

Un circuit électronique servant à produire des codes de détection d'erreur à partir de signaux numériques organisés en blocs de données en série, le code d'erreur étant dérivé des coefficients d'un polynôme résiduel obtenu par division, au moyen d'un polynôme diviseur, d'un polynôme dividende dont les coefficients sont les bits de chaque bloc série, est mis en oeuvre par rétroaction par l'intermédiaire d'additionneurs à l'intérieur d'un registre à décalage. La remise à zéro du registre nécessaire au début de chaque bloc de données série et le chargement d'un premier bit d'information du bloc sont tous deux exécutés dans un unique intervalle d'horloge, le registre étant formé de bascules à deux entrées possibles, l'une étant utilisée pendant la réception du premier bit d'un bloc pour traiter ce bit et mettre le reste du registre dans un état défini, et l'autre servant pendant le traitement des bits qui restent.

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