Electronic circuit package

H - Electricity – 01 – L

Patent

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Details

H01L 23/522 (2006.01) H01L 23/02 (2006.01) H01L 23/12 (2006.01) H01L 23/50 (2006.01) H01L 23/538 (2006.01) H01L 25/065 (2006.01) H01L 25/18 (2006.01)

Patent

CA 2061949

An electronic circuit package has a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips are connected by means of the bus line and are bare chip packaged on a substrate. The chips and the wiring substrate are connected by wiring bonding between pads formed on the chips and the substrate. The substrate may be a multilayer. Preferably, there is an insulating layer partially formed on a surface of the multilayer substrate, and a die bonding ground is formed on a surface of the insulating layer in order to use a portion of the substrate under the ground as a wiring or hole region. At least one of the chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the chips connected to one data bus line being located on one side of the substrate and the chips connected to the other data bus line being located on the other side of the substrate.

Circuit électronique comprenant un substrat de câblage, au moins deux puces à semiconducteurs et un bus. Toutes les puces à semiconducteurs sont connectées au moyen du bus et sont déposées nues sur un substrat. Les puces et le substrat de câblage sont soudés entre des pastilles formées sur les puces et le substrat. Le substrat peut être multicouche. De préférence, une couche isolante recouvre en partie la surface du substrat multicouche, et une masse de fixage recouvre une surface de la couche isolante afin d'utiliser comme câblage ou zone trouée une partie du substrat sous la masse. Au moins une des puces est formée sur la masse de fixage. Le bus comprend de préférence deux lignes de données, les puces connectées à l'une étant situées d'un côté du substrat et les puces connectées à l'autre étant situées de l'autre côté du substrat.

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