Electrostatic discharge protection circuit for an integrated...

H - Electricity – 05 – F

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317/3, 356/66

H05F 3/00 (2006.01) H01L 27/02 (2006.01) H02H 9/04 (2006.01) H05F 3/02 (2006.01)

Patent

CA 1330105

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR AN INTEGRATED CIRCUIT Abstract of the Disclosure A terminal of an integrated circuit is protected from electrostatic discharge voltages at the terminal by a protection circuit which includes a bidirectionally conductive transistor as a discharge current shunting device. A bidirectionally conductive controlled path is provided between the terminal and one of two voltage supply terminals. The transistor has a biassing resistor connected between the terminal and its control electrode. A normally reverse biassed diode is connected between the control electrode and another of the voltage supply terminals. For an n-channel FET or an npn bipolar transistor, when a positive electrostatic discharge is applied to the terminal, a current flowing through the biassing resistor turns on the transistor to provide a discharge path from the terminal to the voltage supply terminal. When a negative electrostatic discharge is applied to the terminal, the diode is forward biassed and a resulting current flow through the biassing resistor turns on the transistor to provide a discharge path from the voltage supply terminal to the terminal. The transistor may be either a symmetrical bipolar transistor or an enhancement mode FET. An embodiment of the circuit for protecting a gallium arsenide integrated circuit (GaAs IC) uses an enhancement mode MESFET and a Schottky barrier diode. For an p-channel FET or a pnp bipolar transistor the polarity of the discharge is reversed. - i -

605439

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