Emitter coupled logic latch circuit

Details Emitter coupled logic latch circuit Emitter coupled logic latch circuit

H - Electricity

03

K

328/130

H03K 19/018 (2006.01) H03K 3/2885 (2006.01) H03K 3/289 (2006.01)

Patent

CA 1307032

ABSTRACT OF THE DISCLOSURE An ECL latch circuit comprises a data input part and a latch part. The data input part includes input transistors coupled in parallel and having bases for respectively receiving an input data and a clock signal, and an output transistor applied with a reference voltage. The data input part samples the input data by the clock signal and outputs a level shifted data signal from a collector of the output transistor. The latch part includes a transistor which has a base for receiving the same clock signal, an emitter coupled transistor pair having bases respectively applied with the reference signal and an output signal of the ECL latch circuit, and a transistor having a base coupled to the collector of the output transistor and an emitter coupled to the base of the latter of the transistor pair.

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