Emitter coupled logic latch with boolean logic input gating...

Details Emitter coupled logic latch with boolean logic input gating... Emitter coupled logic latch with boolean logic input gating...

H - Electricity

03

K

328/138

H03K 3/288 (2006.01) H03K 3/2885 (2006.01) H03K 19/013 (2006.01) H03K 19/086 (2006.01)

Patent

CA 1258299

Abstract of the Disclosure A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.

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