Encoder for multiplexing blocks error protected bits with...

Details Encoder for multiplexing blocks error protected bits with... Encoder for multiplexing blocks error protected bits with...

H - Electricity

04

L

H04L 1/22 (2006.01) H04J 3/02 (2006.01) H04L 1/00 (2006.01)

Patent

CA 2298221

An error detection encoder comprises separation circuitry for separating an input signal into a first sequence of error protected bits and a second sequence of error unprotected bits. Calculation circuitry produces an error check sequence from the first sequence and concatenates the error check sequence to the first sequence to produce a thud sequence. The second sequence may be further separated into a first sub-sequence of higher significant bits and a second sub-sequence of lower significant bits. A multiplexer is provided for segmenting the third sequence into a plurality of first blocks and segmenting the first sub-sequence into a plurality of second blocks corresponding to the first blocks and multiplexing each of the first blocks with a corresponding one of the second blocks to produce a fourth sequence in which the first and the second blocks are arranged in an alternating order. The second sub-sequence is concatenated to the fourth sequence to produce an output sequence for transmission.

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