End-to-end information memory arrangement in a line controller

Details End-to-end information memory arrangement in a line controller End-to-end information memory arrangement in a line controller

H - Electricity

04

Q

344/29

H04Q 3/54 (2006.01) H04L 12/56 (2006.01)

Patent

CA 1193702

- 40 - END-TO-END INFORMATION MEMORY ARRANGEMENT IN A LINE CONTROLLER Abstract A communication method and packet switching system in which packets comprising physical addresses and voice/data information are communicated through the system by packet switching networks which are interconnected by high-speed digital trunks with each of the latter being directly terminated on both ends by trunk controllers. Customer terminals are connected to the switching system by access line controllers which insert the physical addresses into the packets. The line controllers attach to concentrators which are interconnected to the switching networks via high-speed digital trunks. During initial call setup of a particular call, the physical addresses are obtained and stored in the line controllers by the transmission of a call setup packet and call reply packet between the originating and destination line controllers. Each processor inserts into the call setup packet the necessary addressing information to route packets through the associated network. Each network comprises stages of switching nodes which are responsive to the physical addresses in a packet to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols.

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