Energy economized pass-transistor logic circuit and full...

Details Energy economized pass-transistor logic circuit and full... Energy economized pass-transistor logic circuit and full...

H - Electricity

03

K

H03K 19/094 (2006.01) G06F 7/50 (2006.01) H03K 19/00 (2006.01) H03K 19/0948 (2006.01)

Patent

CA 2240288

Disclosed is an energy economized pass-transistor logic having a level restoration circuit (50) free from leakage and a full adder using the same. The logic comprises a functional block (10) having a plurality of n type FET's (MI...M4), for performing at least one logical function of inputs (12, 14, 16, 18) to generate two complementary signals (20, 22), the complementary signals (20, 22) being a weak high level signal and a strong low level signal; and a level restoration block (50) having first and second CMOS inverters (52,54), for restoring the weak high level signal to a strong or full high level signal and preventing a leakage current flowing through one of the first and the second CMOS inverters (52,54) where the weak high level is applied.

L'invention porte sur un circuit logique à transistors de chute économisant l'énergie qui comprend un circuit de rétablissement de niveau (50) sans fuite et sur un additionneur complet utilisant ce circuit. Celui-ci comprend un bloc fonctionnel (10) contenant une pluralité de FET de type n (M1, ..., M4) utilisée pour effectuer une opération logique sur des signaux d'entrée (12, 14, 16, 18) qui produit des signaux complémentaires (20, 22) constitués d'un signal faible à niveau élevé et d'un signal fort à niveau bas, ainsi qu'un bloc de rétablissement de niveau (50) contenant un premier et un second inverseur CMOS (52, 54) utilisés pour transformer le signal faible à niveau élevé en un signal fort à niveau élevé et pour empêcher les fuites de courant dans celui des deux inverseurs CMOS (52, 54) où le signal faible à niveau élevé est appliqué.

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