Enhanced cpu microbranching architecture

Details Enhanced cpu microbranching architecture Enhanced cpu microbranching architecture

G - Physics

06

F

354/230.71

G06F 9/22 (2006.01) G06F 9/26 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1224881

ABSTRACT Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit the extra lines which enter the pipeline on a branch. A default branch path can be taken for a test result not yet available and can be replaced with a correct branch target during a clock pause if the test result is false. A return address stack is provided with decoupled loading and pushing to accommodate the two branching speeds. Microcode can specify loading the return address stack with a literal or register value to allow vectored branching and return to a desired line after a delayed call.

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