Enhanced high performance pci

Details Enhanced high performance pci Enhanced high performance pci

G - Physics

06

F

G06F 13/368 (2006.01) G06F 13/00 (2006.01) G06F 13/38 (2006.01)

Patent

CA 2236060

A peripheral component interconnect (PCI) bus is adapted for differential signalling. Two signal lines are providing for each bus signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. Enhanced PCI compliant devices include drivers and receivers capable of differential signalling. The resulting bus architecture supports clocking data on both edges as well as source synchronous clocking. The enhanced PCI bus architecture also supports data blocking, pacing, split transactions, and synchronization commands.

L'invention est un bus d'interconnexion d'éléments périphériques (IEP) adapté à la signalisation différentielle. Deux lignes de transmission sont offertes à chaque signal destiné au bus et l'information est codée sous la forme du signe ou de la grandeur de la différence de tension entre ces deux lignes de transmission. L'invention porte sur des dispositifs IEP améliorés comportant des circuits d'attaque et de réception pouvant utiliser la signalisation différentielle. L'architecture de bus résultante permet de synchroniser les données avec les deux flancs du signal, ainsi que de se synchroniser sur la source. Cette architecture de bus IEP améliorée permet également d'utiliser des instructions de blocage de données, de régulation du trafic, de fractionnement des transactions et de synchronisation.

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