H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/114, 356/126
H01L 29/94 (2006.01) H01L 21/28 (2006.01) H01L 21/82 (2006.01) H01L 21/8242 (2006.01) H01L 27/108 (2006.01)
Patent
CA 1088676
ENHANCEMENT-MODE FETS AND DEPLETION-MODE FETS WITH TWO LAYERS OF POLYCRYSTALLINE SILICON Abstract of the Disclosure Enhancement-mode field-effect transistors (FETs) and depletion-mode FETs are provided on the same semicon- ductive substrate using five basic, lithographic, pattern- delineating steps. The five lithographic masking steps delineate in order: (1) the field isolation regions; (2) the enhancement-mode FET gate electrodes; (3) the depletion-mode FET gate electrodes; (4) contact holes or vias to FET source and drain regions and to depletion- mode FET gates; and (5) the high electrical conductivity metallic-type interconnection pattern. The low-concentration doping required to form the depletion- mode channel regions is provided after the second but before the third pattern delineation step, while the high- concentration doping to form the source and drain regions is provided after the third pattern delineation step. In order to obtain the desired device structure, it is necessary to use two separately defined polycrystalline silicon regions for the gate electrodes of the enhancement-mode and depletion- mode FETs. Using the five basic lithographic masking steps, -1- FET integrated circuits can be fabricated that contain both enhancement-mode and depletion-mode FETs intercon- nected as desired.
281849
International Business Machines Corporation
Ogilvy Renault Llp/s.e.n.c.r.l.,s.r.l.
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