Entry control store for enhanced cpu pipeline performance

Details Entry control store for enhanced cpu pipeline performance Entry control store for enhanced cpu pipeline performance

G - Physics

06

F

354/230.7

G06F 12/06 (2006.01) G06F 9/22 (2006.01) G06F 9/26 (2006.01)

Patent

CA 1227578

ABSTRACT A control store arrangement is provided wherein an entry point table is provided with a macroinstruction from a next instruction register or similar device and supplies a pointer to a control store containing the microcode for the second line of the macroinstruction. In addition, the infor- mation which addresses the entry point table also addresses an entry control store which contains the information for the first microinstruction for each macroinstruction. The control store contains all microcode for subsequent microinstructions for each macroinstruction. A bit field preferably located in the next to the last line of microcode of each microinstruc- tion enables a mechanism to connect the entry control store rather than regular control store to a shared bus only at the time its contents are needed to implement the first line or microcode for a given macroinstruction. In this manner, execution of each macroinstruction may be begun a clock cycle earlier than is possible using prior art control store arrange- ments.

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