Equalizing pulse removal circuit

Details Equalizing pulse removal circuit Equalizing pulse removal circuit

H - Electricity

04

N

350/86

H04N 5/04 (2006.01)

Patent

CA 1158356

- 20 - Abstract of the Disclosure There are provided circuits for removing the equivalent pulses from the video signal. A composite sync signal separated from a video signal is applied to a gate circuit, so that only horizontal sync pulses are extracted. The gate pulse applied to the gate circuit is formed in the following manner. Clock pulses of a frequency 175/4 fH (fH: a horizontal scanning frequency and about 15,734 KHz), for example, is frequency-divided in-to a signal of a frequency 175/256 fH by a frequency divider. A reset circuit processes the frequency-divided output signal, the delayed sync signal and the inverted composite sync signal to form pulses in synchronism with the horizontal sync pulses. The pulses thus obtained reset the frequency divider. At the same timing of the pulse generation from the reset circuit, a gate pulse generating circuit generates pulses whose pulse widths are longer than the pulse widths of the horizontal pulses, which in turn are applied as tile gate pulse to the gate circuit.

371190

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