H - Electricity – 03 – M
Patent
H - Electricity
03
M
H03M 13/00 (2006.01) H03K 7/00 (2006.01) H03M 13/15 (2006.01) H03M 13/25 (2006.01) H04L 1/00 (2006.01) H04L 1/22 (2006.01) H04L 27/18 (2006.01)
Patent
CA 2210299
An error-correcting code generating circuit includes a shift register incarnating a generating polynomial, an exclusive logical sum means, and a logical circuit means for performing arithmetic operations on N bits (where N represents an integer not smaller than two) held by said shift register at one time with a clock having a frequency corresponding to 1/N on the basis of N bits (where N represents an integer not smaller than two) inputted in parallel, to thereby generate an error-correcting code of N bits with a single-shot of clock. Because the error correcting code can be generated through the parallel processing, operation can be executed at a low speed with power consumption as involved being reduced.
L'invention est un circuit générateur de codes de correction d'erreurs comportant un registre à décalage contenant un polynôme générateur, un dispositif de réunion logique et un circuit logique servant à effectuer des opérations arithmétiques sur N bits (où N est un entier non inférieur à deux) conservés par ledit registre à décalage à un moment au moyen d'un signal d'horloge dont la fréquence est 1/N pour N bits introduits en parallèle, le tout produisant un code de correction d'erreurs de N bits au moyen d'un signal d'horloge d'une seule salve. Comme le code de correction d'erreurs peut être produit au moyen d'un traitement parallèle, l'opération peut être exécutée à faible débit, ce qui réduit la consommation d'énergie.
Marks & Clerk
Matsushita Electric Industrial Co. Ltd.
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