Error-correcting system

Details Error-correcting system Error-correcting system

G - Physics

06

F

354/224

G06F 11/08 (2006.01) G06F 11/10 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1165893

ABSTRACT OF THE DISCLOSURE An error-correcting system is disclosed, which system is located between a memory and a central processing unit. The system is comprised of a relief bit memory, an ECC (Error Correction Code) logic circuit, a switching circuit and a correction controlling circuit. The ECC logic circuit detects the occurrence of a soft error and a hard error. When a hard error occurs in the memory, the defective memory cell thereof is switched to the relief bit memory. Accordingly, data to be written into the memory or the relief bit memory is switched by means of the switching circuit. Similarly, data to be read from the memory or the relief bit memory is also switched by the switching circuit. The data to be stored in the relief bit memory is validated by means of the ECC logic circuit and the switching circuit. Further, the (n+1) -bit soft and hard errors are reduced to n-bit soft and hard errors by means of the ECC logic circuit and the switching circuit.

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