Error correction coding apparatus

H - Electricity – 03 – M

Patent

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H03M 13/19 (2006.01)

Patent

CA 2602067

An error correction encoder which generates a low-density parity check code (16) from an input information sequence (15) by using a low-density parity check matrix satisfying a specified weighting distribution, wherein a low- density parity check matrix outputting means (13) is provided which outputs the low-density parity check matrix that allows as many rows as satisfying the above specified weighting distribution, each row being provided with as many cyclic substitution matrices as the weight of a row, to continue and is so constituted as to gradually increase or decrease the weight of a row.

La présente invention concerne un codeur de correction d'erreur qui génère un code de vérification de parité à faible densité (16) provenant d'une séquence d'informations d'entrée (15) en utilisant une matrice de vérification de parité à faible densité satisfaisant une pondération spécifiée ; un moyen de production de matrice de vérification de parité à faible densité (13) est prévu pour produire la matrice de vérification de parité à faible densité autorisant autant de lignes que nécessaire pour satisfaire la pondération susmentionnée, chaque ligne étant dotée d'autant de matrices de substitution cycliques que le poids d'une ligne, pour continuer et il est constitué de manière à augmenter ou diminuer graduellement le poids d'une ligne.

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