Error correction in a digital signal transmission system

Details Error correction in a digital signal transmission system Error correction in a digital signal transmission system

G - Physics

06

F

340/74

G06F 11/00 (2006.01) G11B 20/18 (2006.01)

Patent

CA 1139860

ABSTRACT OF THE DISCLOSURE In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a first modulo-two adder to produce a first parity signal. The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a second modulo-two adder to produce a second parity signal, which is fed back to the first modulo-two adder to thereby add it with the information signals. The predetermined number of words of information signals and the first and second parity signals are serially transmitted through a transmission line.

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