Error correction system for difference set cyclic code in a...

H - Electricity – 04 – N

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350/34, 354/223.

H04N 5/00 (2006.01) H03M 13/00 (2006.01) H03M 13/43 (2006.01) H04L 1/00 (2006.01) H04N 7/035 (2006.01)

Patent

CA 1225746

ABSTRACT An error correction system for a difference set cyclic (272, 190) code with 190 data bits and 82 test bits in a coded transmission teletext system which transmits character information on the vertical blanking interval of a television signal has improved peripheral circuits for operating an error correction circuit. The first improvement is to correct only designated packets which are in frame synchronization condition and/or designated by an index register. The second improvement is to handle shortened (L, k) code where L is less than 272, using common hardware. The third improvement is selection of three operational modes of data to be corrected. In the first mode, uncorrected data is supplied by an external circuit, the uncorrected data is stored temporarily in a buffer memory, and corrected data is stored in the buffer memory again to supply external circuit corrected data. Transfer of data between the buffer memory and the error correction circuit is handled by wired logic hardware. In a second mode, uncorrected data and corrected data are provided in a buffer memory but no external circuit is involved. In a third mode, no buffer memory is used, and an external circuit supplies uncorrected data to an error correction circuit directly and receives corrected data directly from the error correction circuit.

477541

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