Error detection and correction capability for a memory system

Details Error detection and correction capability for a memory system Error detection and correction capability for a memory system

G - Physics

06

F

354/223

G06F 11/10 (2006.01) G06F 11/14 (2006.01) G06F 12/12 (2006.01)

Patent

CA 1106066

ABSTRACT OF THE DISCLOSURE A memory system includes a cache store and a backing store. The cache store provides fast access to blocks of information previously fetched from the backing store in response to commands. The backing store includes error detection and correction apparatus for detecting and correct- ing errors in the information read from backing store dur- ing a backing store cycle of operation. The cache store in- cludes parity generation circuits which generate check bits for the addresses to be written into a director associated therewith. Additionally, the cache store includes parity check circuits for detecting errors in the addresses and in- formation read from the cache store during a read cycle of operation. The memory system further includes control apparatus for enabling for operation, the backing store and cache store in response to the commands. The control appara- tus includes circuits which couples to the parity check cir- cuits. Such circuits are operative upon detecting an error in either an address or information read from the cache store to simulate a condition that the information requested was not stored in cache store. This causes the control apparatus to initiate a backing store cycle of operation for read out of a correct version of the requested information thereby eliminating the necessity of including in cache store more complex detection and correction circuits. -1-

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