Error detection and correction system

G - Physics – 06 – F

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354/223

G06F 11/10 (2006.01) H03M 13/19 (2006.01) G06F 11/00 (2006.01)

Patent

CA 1240065

ERROR DETECTION AND CORRECTION SYSTEM Abstract of the Disclosure An error detection and correction apparatus including a transmission bus for transmitting multi- bit data signals and multi-bit error correction code signals generated responsive to the multi-bit data signals in accordance with a modified Hamming code technique. Parity generators are connected to the bus for receiving the bits of the data signals and select- ed bits of the error correction code signals in accor- dance with the modified Hamming code technique for determining if a single bit error exists in the data. A two-state comparison gate is connected to the parity generators which has a first state if a single bit error does exist, and a second state if a single bit error does not exist. A separate error detection and correction circuit is provided to detect and correct any single bit errors in the data on the transmission bus. The two-state comparison gate is reset to its second state after the separate error detection and correction circuit corrects any single bit error in the data.

497549

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