Error detection and framing in packets transmitted in a...

Details Error detection and framing in packets transmitted in a... Error detection and framing in packets transmitted in a...

H - Electricity

04

L

H04L 1/00 (2006.01) H04Q 11/04 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2055172

-15- Error Detection and Framing in Packets Transmitted in a Sequence of Fixed-length Cells Abstract A digital error check sequence for detecting errors in messages. The error check sequence has a form such that it is distinguishable from a sequence of padding bits, and can thus be employed to both mark the end of the message and determine whether there was an error in the transmission of the message. In one embodiment, the error check sequence includes a single-bit first field and a cyclic redundancy code (CRC) whose least significant bit is always 1. The value of the first field is chosen such that when it is appended to the message, the result is a CRC with a least significant bit of 1. Also disclosed are methods and apparatus for generating the error check sequence and transmission and receiving systems employing the error check sequence.

Affiliated with

Also associated with

Rating

Error detection and framing in packets transmitted in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error detection and framing in packets transmitted in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error detection and framing in packets transmitted in a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1795226