Esd input protection arrangement

Details Esd input protection arrangement Esd input protection arrangement

H - Electricity

01

L

H01L 23/60 (2006.01) H01L 27/02 (2006.01)

Patent

CA 2115477

An arrangement for protecting an input of a monolithic integrated circuit against ESD events, comprises a thick field bipolar main transistor adapted to breakdown under ESD stress to dissipate ESD energy, a thin field bipolar main transistor adapted to breakdown under ESD stress, and an attenuator resistor. The thin field transistor has a lower breakdown voltage than the thick field transistor whereby for an ESD event of a given polarity, the thin field transistor breaks down before the thick field transistor. During an ESD event current, the thin field device responds rapidly to the fast edge of an ESD transient and thereby shunts current that the thick field device is too slow to respond to.

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