H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/177
H01L 21/465 (2006.01) C23F 4/00 (2006.01) H01L 21/3105 (2006.01) H01L 21/3213 (2006.01) H01L 21/66 (2006.01) H01L 21/768 (2006.01)
Patent
CA 1286801
ETCH BACK DETECTION Abstract of the Disclosure An improved method for the etch-back planarization of interlevel dielectric layers provides for cessation of the etch-back upon exposure of an indicator layer. The indicator layer, usually a metal, metal nitride, or silicon nitride is formed either within the dielectric or over an underlying metallization layer prior to patterning by conventional photolithographic techniques. A sacrificial layer, typically an organic photoresist, is then formed over the dielectric layer. Because of the presence of both relatively narrow and relatively broad features in the metallization, the thickness of the sacrificial layer will vary over features having different widths. As etch back planarization proceeds, the indicator layer which is first encountered releases detectable species into the planarization reactor. Detection of these species indicates that removal of the overlying dielectric layers to a predetermined depth is achieved. By placing the detectable layer over only those regions which are expected to be exposed last, the method can be utilized to indicate the end point of etch back planarization of the interlevel dielectric.
574584
Castel Egil D.
Kulkarni Vivek D.
Riley Paul E.
Castel Egil D.
Fairchild Semiconductor Corporation
Kulkarni Vivek D.
Riley Paul E.
Smart & Biggar
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