Etching of integrated-circuit device metallization and...

Details Etching of integrated-circuit device metallization and... Etching of integrated-circuit device metallization and...

H - Electricity

01

L

356/147

H01L 21/70 (2006.01) H01L 21/3213 (2006.01)

Patent

CA 2004281

- 7 - ETCHING OF INTEGRATED-CIRCUIT DEVICE METALLIZATION AND RESULTING DEVICE Abstract Prior to photolithographic patterning, metallization layers deposited in the manufacture of integrated-circuit devices preferably are planarized by over-all etching. In the interest of monitoring such etch process - for the sake of leaving a residual layer having precisely specified thickness, a metallization layer preferably has sublayered structure whose removal can be optically monitored sublayer by sublayer, e.g., by so-called laser trace.

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