Fabrication of complementary patterns for exposing...

Details Fabrication of complementary patterns for exposing... Fabrication of complementary patterns for exposing...

H - Electricity

01

L

356/147

H01L 21/70 (2006.01) G03F 1/14 (2006.01) G03F 1/16 (2006.01) H01L 21/027 (2006.01)

Patent

CA 2032413

For the fabrication of semiconductor chips with an increasing number of electrical elements it is necessary that the geometry of the elements becomes smaller and smaller. For that purpose, lithographic techniques have been developed using x-rays, electron or ion beams. Especially for particle beams, self-supporting masks are stringent with the consequence that it is not possible to fabricate, for example, a ring-shaped structure with one mask. This mask stencil problem is solved by exposing the chip with two complementary masks. The present application relates to a method for automatically splitting one layout into two complementary patterns for the two masks. The method determines all corners of the layout which extend into a hole representing area of the masks. A stability criterion is carried out for the corners, with the consequence that only unstable corners are used for cutting the hole representing area into sections. Subsequently the sections are distributed onto the two patterns alternatively.

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