Fabrication of devices having thin dielectric layers

Details Fabrication of devices having thin dielectric layers Fabrication of devices having thin dielectric layers

H - Electricity

01

L

356/149, 117/86,

H01L 21/285 (2006.01) H01L 21/316 (2006.01) H01L 21/321 (2006.01)

Patent

CA 1297764

- 10 - DEVICES FABRICATION OF/HAVING THIN DIELECTRIC LAYERS Abstract Certain devices require a high quality thin (<25 nanometer) dielectric layer formed on a deposited silicon layer. Applications include capacitor dielectrics in dynamic memories and linear devices. In another application, an electrically erasable programmable read only memory (EEPROM) uses an SiO2 layer between the write gate and the floating gate. The present technique oxidizes amorphous silicon under conditions that suppress grain growth to produce a higher quality oxide than that achieved with conventional furnace oxidation of polysilicon. Rapid thermal oxidation is one method of practicing the technique .

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